The present invention relates to the field of semiconductors, and in particular the use of polysilicon gates.
As the geometries of semiconductor devices have decreased, the thickness of the gate dielectric has similarly decreased. Accordingly, problems arising with the use of ever-thinner gate dielectrics have become more pressing. One problem is that as the gate dielectric is thinned, the boron dose for p-channel devices has to be reduced to avoid, for example, massive boron penetration through the gate dielectric. Another problem with device scaling is that the poly depletion effect becomes significant when the depletion layer thickness is compared to the thin gate dielectric thickness. In addition, for polysilicon gates grains form columnar structures that enhance both penetration and deactivation of boron. Similar considerations apply to phosphorus-doped polysilicon gates.
Additionally, the anneal temperature has to be reduced for thin polysilicon gates, also to avoid massive boron penetration into the gate dielectric. Annealing at a lower temperature reduces activation. Moreover, source/drain junctions are another consideration.
As long as it is desired to use polysilicon for gate material, a process that would allow very thin gates while minimizing depletion and penetration effects is desirable. At the same time, a process that increases conductivity of the gate electrode is always desirable. Accordingly, a need exists for a process to minimize gate depletion and dopant penetration, and to increase conductivity, while allowing for higher anneal temperatures to increase activation.